Soft-start control system and method for an isolated dc-dc converter with secondary controller

ABSTRACT

A DC-DC converter for supplying a gradually increasing voltage via a soft start circuit from a first powered domain to a second unpowered domain. The powered domain may be connected to a primary winding of a first transformer, and the unpowered domain may be connected to the secondary winding of the first transformer. The unpowered domain may respond to an applied voltage from the soft start circuit by supplying a feedback signal to the powered domain via a feedback circuit. The feedback signal indicating the power supplied from the secondary winding of the first transformer to the unpowered domain is satisfactory.

PRIORITY

This application claims priority to provisional U.S. Patent Application Ser. No. 61/406,499 filed on Oct. 25, 2010, the content of which is incorporated herein in its entirety.

BACKGROUND

Isolated DC-DC converters include power transfer circuitry to power an otherwise unpowered voltage domain from a powered voltage domain. The power transfer typically occurs across an isolation barrier. The converter includes a pair of electrically-isolated voltage domains, one of which is powered. The powered voltage domain may transfer power to an otherwise unpowered voltage domain that drive circuitry in the unpowered voltage domain.

DC-DC converters commonly begin operation at a nominal voltage in the unpowered voltage domain that must build to a voltage level that allows for proper operation of the DC-DC converter. However, when the converter is initially started, the circuit components of the converter experience a large in-rush of current. The in-rush current delays proper operation of the DC-DC converter because the converter circuit components are delayed from properly operating until the ringing resulting from the large in-rush current subsides.

There is a need for a system and method to reduce the in-rush current and allow for a more gradual transition between starting operation and continued operation of the DC-DC converter.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a block diagram of a power transfer and control system 100 according to an embodiment of the present invention.

FIG. 2 illustrates an exemplary schematic diagram of an isolated DC-DC converter according to an embodiment of the present invention.

FIG. 3 illustrates an exemplary integrated chip implementation of a DC-DC converter method according to an embodiment.

FIG. 4 illustrates an alternative implementation of a DC-DC converter in which the power transformer is shown implemented off chip.

DETAILED DESCRIPTION

An isolated DC-DC converter is provided that may control the start up voltage to smoothly transfer power from a powered voltage domain to an unpowered voltage domain via a first transformer. The smooth transfer of power is controlled by a feedback control signal that may be transferred across the isolation barrier via a second transformer from the unpowered domain to the powered domain. The feedback signal may indicate whether a voltage induced in the unpowered domain is within proper operating limits. The powered domain may include control circuits that, responsive to the feedback signal, may alter drive signals applied to the first transformer to correct any abnormalities in the voltage induced in the unpowered domain.

A method for soft starting a DC-DC converter is provided. The method may include outputting a soft start signal to cause a power transformer to provide a power supply signal to a DC-DC converter controller. The soft start signal may gradually increase in amplitude. A blocking circuit may compare the power supply signal to a reference signal. Based on the result of the comparison, the blocking circuit may prevent the controller output signal from being applied to a first side of a feedback transformer. When the result of the comparison indicates that the power supply signal is within a certain threshold of the reference signal, the blocking circuit may output a signal indicating that the power supply signal is within the threshold of the reference signal. In response, a controller may apply its output signal to a first side of the feedback transformer. A second side of the feedback transformer may output a signal that may be detected by an activity detector circuit. The activity detector circuit may in response output an activity signal that stops the outputting of the soft start signal.

FIG. 1 illustrates a block diagram of a power transfer and control system 100 according to an embodiment of the present invention. The system 100 may include a pair of voltage domains 110, 120 each domain electrically isolated from the other. The system may include a feedback transformer 130 and a power transformer 140 that bridge an isolation barrier IB provided between the two domains 110, 120.

As illustrated, circuits in the first domain 110 may be powered by a locally provided power source, shown as VDD. The second domain 120 may be unpowered except for power delivered to it from the first domain 110 via the power transformer 140. Circuits in the second domain may be powered by the energy delivered via the power transformer 140. The second domain, once powered, may also supply power to a load device CLOAD. A feedback transformer 130 with a primary winding in the unpowered second domain 120 may pass a signal via a secondary winding in the first powered domain 110.

The system 100 also may include various circuits to control power exchange between the two domains 110 and 120. In the powered domain 110, the control circuits may include a soft start circuit 132, routing logic 134, driving amplifiers 141, 143, a feedback processor 135, a receiver 131 and an activity detector 136. Control circuits in the unpowered domain 120 may include a feedback controller 165, a blocking circuit 167, control logic 170, and a driver 138.

In the powered domain 110, a soft start circuit 132 may output a gradually increasing duty signal to start powering the second, unpowered second domain 120. The soft start circuit 132 of the system 100 may generate a pulse width modulated (PWM) signal based on a signal (i.e. periodic, aperiodic, increasing amplitude and/or frequency) and a reference voltage signal, for example, a sawtooth waveform and a ramping reference voltage. As a result, the PWM signal may gradually increase in amplitude based on the ramping reference voltage, thereby providing a graceful transition of power to the unpowered domain. The PWM signal may be output by the soft start circuit 132 to the routing logic 134. The routing logic 134, responsive to a control signal input from the activity detector 136, may route signals from one of the feedback processor 135, or the soft start circuit 132 to the power transformer 140. The routing logic 134 may operate in response to the signal received from the soft start circuit 132 to provide a signal suitable for transformation by the power transformer 140. The routing logic 134 may include multiplexer 133 and demultiplexer 137. The multiplexer 133 and demultiplexer 137 of routing logic 134, in response to a control signal, may operate to provide a signal of appropriate frequency and magnitude to drive amplifiers 141 and 143. The driving amplifiers 141, 143 may provide an amplified signal for driving the power transformer 140. In fly back or forward converter configurations, a single switch and driver may be suitable. In these and some other cases, a single driving amplifier may be utilized when a single switch is used to supply a power signal to the power transformer. In such configurations, routing logic 134 may not need multiplexer 133 and/or demultiplexer 137.

The power transformer 140 may transform the amplified signal from the first, powered domain 110 as an output to the second, unpowered domain 120. In response to the alternating drive signals, the power transformer 140 may provide a transformed output signal to the rectifier 145. The transformed power supply signal may be rectified by rectifier 145 to a DC signal VOUT. The rectifier 145 may rectify the signal output from the power transformer 140, and may output an output signal VOUT. The VOUT may be output from the converter 100, and may be applied to the feedback controller 165 and to the blocking circuit 167. The feedback controller 165 may generate a feedback signal based on the output voltage VOUT signal. For example, the feedback signal may be a pulse width modulated (PWM) signal representing a magnitude of VOUT. The output VOUT signal may also be used as a supply voltage for various circuits such as driver 138, feedback controller 165 and blocking circuit 167.

The feedback controller 165 may receive the output DC signal VOUT, and may compare the signal VOUT to a reference signal (not shown). Based on the results of the comparison, the feedback controller 165 may output an output signal, such as a pulse width modulated (PWM) signal, to the control logic 170. The feedback controller 165 may be, for example, a type III controller. The blocking circuit 167 may also monitor the output DC signal VOUT by comparing VOUT to a reference signal, and output a signal based on the comparison. The blocking circuit 167 may output a signal indicating to the control logic 170 to allow the signal generated by the feedback controller 165 to be applied to the driver 138 when, for example, the power supply voltage (i.e. VOUT) is within a threshold of a reference voltage to which VOUT is compared.

The control logic 170 may, for example, receive both the PWM signal output by the feedback controller 165 and the signal output from the blocking circuit 167. Based on the output from the blocking circuit 167, the control logic 170 may either allow or prevent the signal generated by the feedback controller 165 to be applied to the driver 138. The control logic 170 may pass the feedback signal from the feedback controller 165 based on the blocking control signal received from the blocking circuit 167. The driver 138 may supply a drive signal to the feedback transformer 130. The feedback transformer 130 may transform the drive signal from the driver 138.

The signal generated by the feedback transformer 130 may be applied across the isolation barrier 113 to the powered domain to receiver 131. The receiver 131 may amplify the transformed signal, and apply it to the activity detector 136 and feedback processor 135.

The activity detector 136 may compare the signal received from receiver 131 to a reference voltage (that may be different from or have a magnitude substantially the same as the reference voltage used by blocking circuit 167). If the results of the comparison indicate that the voltage VOUT in the unpowered domain is not sufficient (e.g. the voltage is not at a high enough magnitude, the activity detector 136 may output an activity control signal indicating the result to the routing logic 134. Based on the routing logic 134 may prevent the activity control signal from the activity detector 136, the PWM signal from the soft start circuit 132 from being passed out of the routing logic 134. For example, in response to the activity control signal received from the activity detector 136, the routing logic 134 may stop processing the signal received from the soft start module 132, and begin passing and processing the signal received from the feedback processor 135.

The routing logic 134 may continue to output the signal from the soft start circuit 135 until the activity detector 136 indicates the signal from the feedback transformer 130 is to be used in place of the soft start circuit 135.

The feedback processor 135 may generate control signals for driving drivers 141 and 143 of the power transformer 140 in response to feedback signals received from the feedback transformer 130. The signal from the feedback processor 135 may be any type of or any form of signal, for example, a PWM signal. In the illustrated configuration, feedback processor 135 may generate two signals, one for each driver 141 and 143. Various implementations may be envisioned. An exemplary circuit configuration will be discussed in more detail with reference to FIG. 2.

FIG. 2 illustrates an exemplary schematic diagram of an isolated DC-DC converter according to an embodiment of the present invention. The isolated DC-DC converter 200 may have a powered domain 201 and unpowered domain 202. The powered domain 201 and the unpowered domain 202 may be separated by an isolation barrier 290. The isolation barrier may be bridged by a power transformer 230 and feedback transformer 270. The power transformer 230 may provide power across the isolation barrier 290 to the unpowered domain 202, and the feedback transformer 270 may provide feedback signals from the unpowered domain 202 across the isolation barrier 290 to the powered domain 201. The powered domain 201 may include a soft start circuit 210, start logic 220, power switches 235, a power transformer 230 and an activity detector 280. The unpowered domain 202 may include a feedback controller 240, control logic 250, a blocking circuit 260, and a feedback transformer 270. Additional circuit components such as capacitors and resistors may also be included. The activity detector 280 may include logic, for example, a D flip-flop, and may have inputs from the feedback transformer 270, and outputs to the start logic 220.

The soft start circuit 210 may include a current source, a capacitor, an input for a reference waveform, and an amplifier. The start logic 220 may include a multiplexer 225, an S-R flip-flop 222, a NOR gate 229, a T flip-flop 221, circuit protection elements (short circuit protection, undervoltage lock-out (UVLO), thermal shutdown 227, pulse-by-pulse generator 223, and dual-NOR gates 224. The power transformer 230 may have a center-tap power supply connection, and may, for example, be connected to rectifying circuitry to provide a DC output signal.

The controller 240 may be a feedback controller connected to a voltage divider network, and may, for example, have capacitors and other circuit components connected. Controller 240 may be a type III controller. A reference voltage source, a reference waveform source and a clock signal may be connected to the controller 240. These may also be powered via the power transformer 230.

The control logic 250 may, for example, include an S-R flip-flop 252 and cascaded OR gates 255, 257 and 259. Other combinations of flip-flop circuits and logic gates may be used to provide the same or similar functionality as control logic 250.

The blocking circuit 260 may include a comparator 264 for comparing the power transformer output voltage to a reference voltage. The blocking circuit 260 may also be configured with a D flip-flop 268, an undervoltage lockout (UVLO) 262, and outputs to the control logic 250.

The feedback transformer 270 may include inputs from the control logic 250, and may have an output for providing a feedback signal. The feedback transformers 270 may also have an output to the start logic 220 and the activity detector 280.

The exemplary DC-DC converter 200 may operate as described in the following example. At start up of the DC-DC converter 200, an output voltage VOUT may not be present at the output of the power transformer 210, and no signal may be present at the feedback back transformer 270. In other words, the powered domain 201 has not begun to provide power to the unpowered domain 201. In response to a control signal, a current source within soft start 210 may begin charging a capacitor, which may have a voltage VCAP. By operation of a shorting switch, the capacitor may be periodically discharged, and the capacitor begins recharging causing a varying voltage to be applied to an amplifier. The voltage of the capacitor may be compared, for example, by the amplifier to a reference voltage waveform. Based on the result of the comparison, a output waveform, such as a pulse wave modulated (PWM) waveform with a gradually increasing amplitude may be generated, and output from the soft start circuit 210 as a soft start waveform. In addition, the signal from the soft start 210 may be a PWM signal that may be approximately double the frequency needed to generate a suitable output voltage VOUT from the power transformer 230.

The gradually-increasing soft start waveform may be applied to a multiplexor 225 in the start logic 220. The multiplexor 225 may have both a control input and a signal input from the activity detector 280. Based on the present control signal from the activity detector 280 to the multiplexor 225, either the PWM waveform from the soft start circuit 210 or the PWM signal from the feedback transformer may be used.

Specifically, since the output voltage VOUT may not be immediately present at the output, the activity detector 280 may not output a signal to the start logic 220 because an appropriate level of power has not yet been supplied to the unpowered domain 202. In the absence of an activity detector 280 signal, the start logic 220 may only passes the signal received from the soft start circuit 210.

The multiplexor 225 may apply the PWM signal from the soft start 210 to both the reset (R) terminal of the S-R flip-flop 222 and an input of OR gate 229. The pulse-by-pulse circuit 223 may apply a signal to the set (S) terminal of the S-R flip-flop 222. In response, the output (Q) of the S-R flip-flop 222 may be applied to a first terminal of the pulse-by-pulse OR gate 229. The PWM signal from the soft start 210 may be applied to a second terminal of the OR gate 229.

A frequency of the PWM signal from the soft start 210 may not change, the PWM duty may have a pulse on time that can be truncated by operation of the pulse-by-pulse circuit 223, if, for example, a current limit is passed. When the pulse-by-pulse circuit 223 applies a signal to the set (S) terminal of the S-R flip-flop 222, both the Q signal and the soft start PWM signal 210 may be applied to the OR gate 229.

The output of the OR gate 229 may be applied to a T terminal of the T flip-flop 221, and to one of a plurality of inputs to each of the power switch driving dual-NOR gates 224. The T flip-flop 221 may toggle the output states of its outputs Q and QB in response to the signal received from the OR gate 229.

If no protection (e.g., short circuit protection, undervoltage lock-out (UVLO), and thermal shutdown 227) circuit output is activated (i.e. stays OFF), the power switch driving dual-OR gates 224 may simply respond to the signals from toggled outputs (Q and QB (Q-bar)) of the T flip-flop 221. The protection circuits, short circuit protection, UVLO, thermal shutdown 227 stay on when a fault condition occurs thereby preventing dual-NOR gates 224 from changing states.

The driving signals output from the power switch driving dual-NOR gates 224 may be alternately applied to gate terminals of the power switches 225. The power switches 225 may alternately conduct thereby forming a current path from the center tap voltage applied to the power transformer 230 to ground. With an alternating current path formed, the power transformer 230 may gradually charge to generate an output voltage VOUT. The power switches 225 may have a varying duty cycle of, for example, approximately 30% on/70% off for a first switch and a duty cycle, for example, of approximately 30% on/70% off with a delay of 50% for a second switch. This allows for a gradual rise in the applied voltage and minimizes in-rush current. Of course, other duty cycles that may provide suitable performance to gradually generate an output voltage in the unpowered domain may also be used.

A rectifying circuit connected to the power transformer 230 rectifies the output AC voltage to a DC voltage (e.g. 3.3 or 5 volts, the power transformer 270 can either maintain the same voltage, step up, or step down the voltage to the unpowered domain 202). Initially, the output DC voltage VOUT may be below the desired output voltage. The output DC voltage VOUT may be applied to circuit components (resistors and capacitors), which may form voltage dividers and/or feedback circuits. The error amplifier may include VOUT clamps to allow the error amplifier output to settle more quickly. A reduced voltage, such as VRAIL, may be supplied to the controller 240. The controller 240 may receive the voltage VRAIL as an input to the error amplifier 245 where the VRAIL voltage is compared to a reference voltage. The results of the comparison by error amplifier 245 may be provided to a PWM comparator 241 that may have an alternating input signal (e.g., saw tooth) received from a waveform generator 242. The output of the PWM comparator 241 may be a PWM signal.

The control logic 250 may have an input for the PWM signal from the PWM comparator 241, and an input from a clock signal provided by the waveform generator 242. The PWM signal may be applied to the S terminal of an S-R flip-flop 252. The clock signal from waveform generator 242 may be applied to an R terminal of the S-R flip-flop in the control logic 250, and a first OR gate 255 in the control logic 250. The output terminal (Q) of the S-R flip-flop may be output to a terminal of the first OR gate 255. The output of the first OR gate 255 may be applied to a first input of a second OR gate 257. A second input of the second OR gate 257 may be received from a D flip-flop 268 of the blocking circuit 260. The D flip-flop 268 may have a voltage signal input to its D input and a pulse-frequency modulation (PFM) comparator 264 output connected to a clock (CLK) terminal of the D flip-flop 268.

The inputs to the PFM comparator 264 may be the reference voltage from the controller 240 and the DC voltage VRAIL from, for example, the voltage divider circuit connected to the rectifier of the power transformer 210. Until the DC voltage output VOUT by the power transformer (and the voltage VRAIL) is within a predetermined threshold of the reference voltage (i.e., exceeds a PFM threshold), the D flip-flop 268 may apply a signal to the second terminal of second OR gate 257. This prevents the second OR gate 257 from outputting a varying signal. Generally, when the output DC voltage VOUT is within the predetermined threshold of the reference voltage, the D flip-flop 268 allows the blocking circuit 260 to assert the blocking control signal to the second OR gate 257. The second OR gate 257 may have an output connected to a third OR gate 259. The third OR gate 259 may be used to implement a UVLO protection circuit 262. If there is an under voltage condition, UVLO protection circuit 262 may assert a signal to OR gate 259, which prevents the OR gate 259 from changing states. With no signals applied to OR gates 257 and 259 by the blocking circuit 260, or the UVLO protection circuit, a varying signal may be applied to the feedback transformer 270. The feedback transformer 270 may transform the varying signal applied from control logic 250, and output a varying signal on its secondary winding. The varying signal output by the feedback transformer 270 may be applied to the activity detector 280 and the start logic 220 of the powered domain 201.

In the powered domain 201, the activity detector 280 may be implemented using digital logic, for example, a D flip-flop. The D flip-flop may receive the alternating signal at a clock (CLK) terminal. Based on the received alternating signal, an output (Q) of the D flip-flop may supply a control signal to a multiplexer 225 of the start logic 220. The output Q signal may cause multiplexer 225 to select the input from the feedback transformer 270 instead of the input from the soft start circuit 210. This indicates that the power supplied to the unpowered domain 202 is within a threshold of the desired voltage (e.g. substantially 5 volts). As a result, the signal from the soft start 210 is no longer applied, and the voltage in the unpowered domain was permitted to rise gracefully.

The above is an exemplary detailed description of the operation of start logic 220, controller 250, blocking circuit 260 operations, and control logic 270 that may be used to implement an embodiment of the present invention. Other logic may be designed to implement similar operations and functionality by one of ordinary skill in the art.

FIG. 3 illustrates an exemplary integrated chip implementation of a DC-DC converter method according to an embodiment. The on-chip DC-DC converter 300 may include inputs for an input voltage VCC, an output for output voltage VOUT, inputs/outputs (I/OA-I/OD) for data channels A-D. The components of on-chip DC-DC converter 300 may include a power transformer 310, a rectifier 345, a regulator 347, a controller and control logic 349, a feedback transformer 320, secondary data input/output (I/O) 355, channel transformers 3301-330D, primary data I/O 365, and primary converter drive 305. The power supply voltage VCC may be provided to the power transformer 410 and as an input to converter primary drivers 405. The on-chip DC-DC converter 300 may operate as explained above with respect to FIGS. 1 and 2. Functions shown in FIGS. 1 and 2 may have been combined in FIG. 3. For example, the primary converter driver 305 of on-chip DC-DC converter 300 may include a soft start circuit, an activity detector, routing logic, and power switches as described with reference to FIGS. 1 and 2. In addition, the regulator 347 may include components (e.g. voltage clamp) that may be formed on chip, and may only supply voltages to the controller and control logic 349. In contrast, the regulation functions may occur within the controller of FIGS. 1 and 2. Other embodiments may include configurations where only portions of the components are formed on a single integrated chip.

FIG. 4 illustrates an alternative exemplary implementation of a DC-DC converter in which the power transformer is shown implemented off chip according to an embodiment of the present invention. For example, a power transformer 410, and a rectifier 445 may be located off chip. The components of the exemplary DC-DC converter 400 may include a regulator 447, a controller and control logic 449, a feedback transformer 420, secondary data input/output (I/O) 455, channel transformers 430A-430D, primary data I/O 465, and converter primary drive 405. The power supply voltage VCC may be provided to the power transformer 410 and as inputs to converter primary drivers 405. The DC-DC converter 400 may have inputs for power from VCC and from rectifier 445 and the secondary side of power transformer 410.

The DC-DC converter 400 may operate as explained above with respect to FIGS. 1 and 2. Functions of some circuits shown in FIGS. 1 and 2 may have been combined in components of FIG. 4. For example, the converter primary driver 405 of on-chip DC-DC converter 400 may include a soft start circuit, an activity detector, routing logic, and power switches as described with reference to FIGS. 1 and 2. In addition, the regulator 447 may include components that may be formed on chip, and may only supply voltages to the controller. The controller and control logic 449 may provide the control functions as described with reference to the controller of FIGS. 1 and 2. Similarly, the regulation functions may also be performed by the controller and control logic 449. Other embodiments may include configurations where only portions of the components are formed on a single integrated chip. The present embodiment may provide the advantage of leaving high voltage components off of the integrated circuit chip, and also allowing more chip real estate for inclusion of, for example, additional data channels.

Several features and aspects of the present invention have been illustrated and described in detail with reference to particular embodiments by way of example only, and not by way of limitation. Those of skill in the art will appreciate that alternative implementations and various modifications to the disclosed embodiments are within the scope and contemplation of the present disclosure. 

1. An isolated DC-DC converter comprising: a pair of transformers, a first transformer and a second transformer; an isolation barrier including the first transformer that provides voltage from a powered voltage domain to an unpowered voltage domain; a feedback control circuit in the powered voltage domain for determining whether a voltage induced in the unpowered domain is within proper operating limits, wherein the determination is based on a feedback signal transferred through the second transformer from the unpowered domain to the powered domain; and control circuits in the powered domain, responsive to the feedback signal, for altering drive signals applied to the first transformer to correct any abnormalities in the voltage induced in the unpowered domain.
 2. The DC-DC converter of claim 1, further comprising: a soft start module in the powered domain, wherein the soft start module generates an output to the first transformer that induces a gradually increasing voltage in the unpowered voltage domain; and a controller in the unpowered domain, wherein the controller disables a feedback generation circuitry in the unpowered domain until the induced voltage is within a predetermined limit of an ideal operating voltage.
 3. The DC-DC converter of claim 2, further comprising: an activity detector in the powered domain for detecting a voltage output from the second transformer, wherein the generated output from the soft start module is output to the first transformer.
 4. The DC-DC converter of claim 1, further comprising: a blocking circuit, in the unpowered domain, for preventing the feedback control circuit from outputting a feedback signal.
 5. The DC-DC converter of claim 1, further comprising: control logic, in the unpowered domain, responsive to inputs from a blocking circuit and the first transformer, wherein the control logic outputs a signal to a primary winding of the second transformer.
 6. An isolated DC-DC converter comprising: a powered domain comprising a primary winding of a first transformer, a secondary winding of a second transformer, a soft start circuit, routing logic, an activity detector, and a feedback processor; an unpowered domain comprising a secondary winding of the first transformer, a primary winding of the second transformer, a rectifier circuit, a feedback controller, a blocking circuit and control logic; and an isolation barrier separating the powered domain from the unpowered domain.
 7. The isolated DC-DC converter of claim 6, the routing logic comprising: a multiplexer having inputs for signals from the soft start circuit and the feedback detector, wherein the multiplexer is controlled by a control signal from the activity detector and the feedback detector generates control signals to drive the primary winding of the first winding.
 8. The isolated DC-DC converter of claim 6, the activity detector comprising: an input from the secondary winding of the second transformer, wherein the signal at the input is based on a signal generated by the control logic in the unpowered domain; an output for controlling the input to the start logic; and an output for providing an input signal
 9. The isolated DC-DC converter of claim 6, the control circuit comprising: logic gates that in based on an output from the blocking circuit allow signals from the feedback controller to pass to the primary winding of the second transformer.
 10. A method for soft starting a DC-DC converter, comprising: outputting a soft start signal causing a power transformer to provide a power supply signal to a DC-DC converter controller; gradually increasing the soft start signal in amplitude; comparing the power supply signal to a reference signal by a blocking circuit; based on the result of the comparison, disable, by the blocking circuit, application of the power supply signal generated by the DC-DC converter controller to a first side of a feedback transformer; when the result of the comparison indicates that the power supply signal is within a certain threshold of the reference signal, outputting from the blocking circuit a signal indicating that the power supply signal is within the threshold of the reference signal; in response to the output signal from the blocking circuit, applying by a controller a modulated form of the power supply signal to a secondary side of the feedback transformer; detecting by an activity detector circuit, a signal output from the secondary side of the feedback transformer in response to the applied modulated power supply signal; and in response, the activity detector circuit outputs an activity signal that stops the outputting of the soft start signal.
 11. The method of claim 10, further comprising: passing the signal output from the secondary side of the feedback transformer to routing logic for application to the power transformer.
 12. A DC-DC converter on an integrated circuit chip, comprising: a power transformer having first and second windings; a converter driver coupled to the first winding the power transformer for applying during start up a gradually increasing driving signal to the first winding of the power transformer; a controller coupled to the second winding of the power transformer for monitoring the power supply signal provided at the second winding of the power transformer; and a feedback transformer having a first winding coupled to the controller and a second winding coupled to the converter driver, wherein a signal generated, in response to a signal generated by the controller, at the second winding of the feedback transformer determines whether the converter driver continues to apply the gradually increasing driving signal to the first winding of the power transformer.
 13. The on-chip DC-DC converter of claim 12, the converter driver comprising: a soft start module that applies the gradually increasing driving signal, wherein the gradually increasing signal has a variable duty cycle; an activity detector for determining whether the signal received from the second winding of the feedback transformer is within a threshold voltage for the DC-DC conversion; and a feedback processor for providing a normal driving signal suitable for driving the power transformer at the threshold voltage for DC-DC conversion.
 14. The on-chip DC-DC converter of claim 12, further comprising: a blocking circuit to prevent the signal generated by the controller from being applied to the first winding of the feedback transformer.
 15. The on-chip DC-DC converter of claim 12, wherein the power transformer is off chip and has terminals for the first and secondary windings to connect to the on-chip converter driver and controller. 